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CS8151 5.0 V, 100 mA Low Dropout Linear Regulator with Watchdog, RESET, and Wake Up
The CS8151 is a precision 5.0 V, 100 mA micro-power voltage regulator with very low quiescent current (400 mA typical at 200 mA load). The 5.0 V output is accurate within 2% and supplies 100 mA of load current with a typical dropout voltage of 400 mV. Microprocessor control logic includes Watchdog, Wake Up and RESET. This unique combination of low quiescent current and full microprocessor control makes the CS8151 ideal for use in battery operated, microprocessor controlled equipment. The CS8151 Wake Up function brings the microprocessor out of Sleep mode. The microprocessor in turn, signals its Wake Up status back to the CS8151 by issuing a Watchdog signal. The Watchdog logic function monitors an input signal (WDI) from the microprocessor. The CS8151 responds to the falling edge of the Watchdog signal which it expects at least once during each wake-up period. When the correct Watchdog signal is received, a falling edge is issued on the wake-up signal line. RESET is independent of VIN and operates correctly to an output voltage as low as 1.0 V. A RESET signal is issued in any of three situations. During power up the RESET is held low until the output voltage is in regulation. During operation if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. And finally, a RESET signal is issued if the regulator does not receive a Watchdog signal within the Wake Up period. The RESET pulse width, Wake Up signal frequency, and Wake Up delay time are all set by one external capacitor CDelay. The regulator is protected against short circuit, over voltage, and thermal runaway conditions. The device can withstand 74 V peak transients, making it suitable for use in automotive environments.
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D2PAK-7 DPS SUFFIX CASE 936AB
1 7 SO-16L DWF SUFFIX CASE 751G
16 1 SOIC-14 D SUFFIX CASE 751A
14 1
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 2 of this data sheet.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
* 5.0 V 2%/100 mA Output Voltage * Micropower Compatible Control Functions

* * *
* *
Wake Up Watchdog RESET Low Dropout Voltage: 400 mV @ 100 mA Low Sleep Mode Quiescent Current (400 mA Typ) Protection Features Thermal Shutdown Short Circuit 74 V Peak Transient Capability Reverse Transient (-50 V) Internally Fused Leads in SO-14L and SO-16L Packages These are Pb-Free Devices
1 Publication Order Number: CS8151/D
(c) Semiconductor Components Industries, LLC, 2008
October, 2008 - Rev. 18
CS8151
PIN CONNECTIONS AND MARKING DIAGRAMS
D2PAK-7 CASE 936AB Delay NC GND GND GND Sense VOUT SO-14L CASE 751A 1 14 CS8151G AWLYWW SO-16L CASE 751G RESET Wake Up GND GND GND WDI VIN NC NC NC GND GND GND Sense VOUT 1 CS8151 AWLYYWWG 16 Delay RESET Wake Up GND GND WDI NC VIN
CS 8151 AWLYWWG 1 Tab = GND Pin 1. VOUT 2. VIN 3. WDI 4. GND 5. Wake Up 6. RESET 7. Delay
A WL Y, YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
VOUT VIN Current Source (Circuit Bias) Overvoltage Shutdown VOUT
Internally connected on D2PAK
Current Limit Sense
Wake Up
Delay
Timing Circuit
Wake Up Circuit
Sense
+- Watchdog Circuit Falling Edge Detector VOUT RESET RESET Circuit Bandgap Reference Thermal Shutdown
Error Amplifier
WDI
GND
Figure 1. Block Diagram
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CS8151
MAXIMUM RATINGS*
Rating Power Dissipation Output Current (VOUT, RESET, Wake Up) Reverse Battery Peak Transient Voltage (60 V Load Dump @ VIN = 14 V) Maximum Negative Transient (t < 2.0 ms) ESD Susceptibility (Human Body Model) ESD Susceptibility (Machine Model) Logic Inputs/Outputs Storage Temperature Range Lead Temperature Soldering Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Notes 2 & 3) Value Internally Limited Internally Limited -15 +74 -50 2.0 200 -0.3 to +6.0 -55 to +150 260 peak 240 peak Unit - - V V V kV V V C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 10 seconds max 2. 60 seconds max above 183C 3. -5C / +0C allowable conditions *The maximum package power dissipation must be observed
ELECTRICAL CHARACTERISTICS (-40C TA 125C, -40C TJ 150C, 6.0 V VIN 26 V, 100 mA IOUT 100 mA,
C2 = 47 mF (ESR < 8.0 W), CDelay = 0.1 mF; unless otherwise specified.) Characteristic Output Section Output Voltage, VOUT Dropout Voltage (VIN - VOUT) Load Regulation Line Regulation Ripple Rejection Current Limit Thermal Shutdown Overvoltage Shutdown Quiescent Current VOUT < 1.0 V IOUT = 200 mA (Sleep) IOUT = 50 mA IOUT = 100 mA (Wake Up) VOUT = 5.0 V, VIN = 0 V 9.0 V < VIN < 16 V 6.0 V < VIN < 26 V, 0 < IOUT < 100 mA IOUT = 100 mA IOUT = 100 mA VIN = 14 V, 100 mA < IOUT < 100 mA IOUT = 1.0 mA, 6.0 V < VIN < 26 V 7.0 V < VIN < 17 V @ f = 120 Hz, IOUT = 100 mA VOUT = 4.5 V - 4.90 4.85 - - - - 60 100 150 50 - - - - 5.0 5.0 400 100 10 10 75 250 180 56 0.4 4.0 12 1.0 5.10 5.15 600 150 50 50 - - 210 62 0.75 - 20 1.5 V V mV mV mV mV dB mA C V mA mA mA mA Test Conditions Min Typ Max Unit
Reverse Current RESET Threshold High (RTH) Threshold Low (RTL) Hysteresis Output Low Output High
RTH VOUT Increasing RTL VOUT Decreasing RTH - RTL 1.0 V < VOUT RTL, IOUT = 25 mA IOUT = 25 mA, VOUT > RTH
VOUT - 0.3 4.5 150 - 3.8
- 4.7 200 0.2 4.2
VOUT - 0.04 4.91 250 0.8 5.1
V V mV V V
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CS8151
ELECTRICAL CHARACTERISTICS (-40C TA 125C, -40C TJ 150C, 6.0 V VIN 26 V, 100 mA IOUT 100 mA,
C2 = 47 mF (ESR < 8.0 W), CDelay = 0.1 mF; unless otherwise specified.) Characteristic RESET Current Limit Delay Time Watchdog Input Threshold High Threshold Low Hysteresis Input Current Pulse Width 0 < WDI < 6.0 V 50% WDI Falling Edge to 50% WDI Rising Edge and 50% WDI Rising Edge to 50% WDI Falling Edge (see Figures 2, 3, and 4) - - - - 0.8 25 -10 5.0 1.4 1.3 100 0 - 2.0 - - +10 - V V mV mA ms RESET = 0 V, VOUT > VRTH (Sourcing) RESET = 5.0 V, VOUT > 1.0 V (Sinking) POR Mode 0.025 0.1 3.0 0.5 12 5.0 1.30 80 7.0 mA mA ms Test Conditions Min Typ Max Unit
Wake Up Output Wake Up Period Wake Up Duty Cycle Nominal RESET High to Wake Up Rising Delay Time Wake Up Response to Watchdog Input Wake Up Response to RESET Output Low Output High Current Limit See Figure 2 See Figure 4 50% RESET Rising Edge to 50% Wake Up Edge (see Figures 2, 3, and 4) 50% WDI Falling Edge to 50% Wake Up Falling Edge 50% RESET Falling Edge to 50% Wake Up Falling Edge, VOUT = 5.0 V 4.5 V IOUT = 25 mA (Sinking) IOUT = 25 mA (Sourcing) Wake Up = 5.0 V Wake Up = 0 V 30 40 15 40 50 20 50 60 25 ms % ms
- -
2.0 2.0
10 10
ms ms
- 3.8 0.025 0.05
0.2 4.2 1.0 -
0.8 5.1 7.0 3.5
V V mA mA
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CS8151
PACKAGE PIN DESCRIPTION
Package Pin # SO-14L 7 8 9 3-5, 10-12 13 14 D2PAK 1 2 3 4 5 6 SO-16L 8 9 11 4, 5, 6, 12, 13* 14 15 Pin Symbol VOUT VIN WDI GND Wake Up RESET
Function Regulated output voltage 5.0 V 2%. Supply voltage to the IC. CMOS/TTL compatible input lead. The Watchdog function monitors the falling edge of the incoming signal. Ground connection. CMOS/TTL compatible output consisting of a continuously generated signal used to Wake Up the microprocessor from sleep mode. CMOS/TTL compatible output lead RESET goes low whenever VOUT drops by more than 6.0% from nominal, or during the absence of a correct watchdog signal. Input lead from timing capacitor for RESET and Wake Up signal. Kelvin connection which allows remote sensing of the output voltage for improved regulation. If remote sensing is not required, connect to VOUT.
1 6
7 -
16 7
Delay Sense
*Pin 6 GND is not directly shorted to the fused paddle GND. The fused paddle GND (pins 4, 5, 12, 13) is connected through the substrate. Pin 6 must be electrically connected to at least one of the fused paddle GND's on the PC board.
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CS8151
TIMING DIAGRAMS
VIN RESET
Wake Up Duty Cycle = 50%
Wake Up
WDI
VOUT POR RESET High to Wake Up Delay Time Power Up Sleep Mode Normal Operation with Varying Watchdog Signal
Figure 2. Power Up, Sleep Mode and Normal Operation
VIN RESET Wake Up WDI
RESET Delay Time
VOUT POR RESET High to Wake Up Delay Time Wake Up Period RESET High to Wake Up Delay Time
Figure 3. Error Condition: Watchdog Remains Low and a RESET Is Issued
RESET Wake Up WDI RTL VOUT Watchdog Pulse Width POR Power Down Watchdog Pulse Width
Wake Up Period
POR
Figure 4. Power Down and Restart Sequence http://onsemi.com
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CS8151
DEFINITION OF TERMS Dropout Voltage: The input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100mV from the nominal value obtained at 14V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. Current Limit: Peak current that can be delivered to the output.
CIRCUIT DESCRIPTION
Functional Description
To reduce the drain on the battery a system can go into a low current consumption mode when ever its not performing a main routine. The Wake Up signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. The nominal output is a 5.0 V square wave with a duty cycle of 50% at a frequency that is determined by a timing capacitor, CDelay. When the microprocessor receives a rising edge from the Wake Up output, it must issue a watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode.
Wake Up WDI
Wake Up Response to WDI
Figure 5. Wake Up Response to WDI
RESET
The first falling edge of the watchdog signal causes the Wake Up to go low within 2.0 ms (Typ) and remain low until the next Wake Up cycle (see Figure 5). Other watchdog pulses received within the same cycle are ignored (Figures 2, 3, and 4). During power up, RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. After the RESET delay, RESET returns high. The Watchdog circuitry continuously monitors the input watchdog signal (WDI) from the microprocessor. The absence of a falling edge on the Watchdog input during one Wake Up cycle will cause a RESET pulse to occur at the end of the Wake Up cycle (see Figure 3). The Wake Up output is pulled low during a RESET regardless of the cause of the RESET. After the RESET returns high, the Wake Up cycle begins again (see Figure 3). The RESET pulse width, Wake Up signal frequency and RESET high to Wake Up delay time are all set by one external capacitor CDelay. Wake Up Period = (4 x 105)CDelay RESET Delay Time = (5 x 104)CDelay RESET High to Wake Up Delay Time = (2 x 105)CDelay Capacitor temperature coefficient and tolerance as well as the tolerance of the CS8151 must be taken into account in order to get the correct system tolerance for each parameter.
Wake Up
Wake Up Response to RESET
Figure 6. Wake Up Response to RESET (Low Voltage)
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CS8151
APPLICATION NOTES
Operation Without Watchdog
The CS8151 can be operated without the watchdog functionality by connecting the WDI and Wake Up Pins. This will eliminate false resets from occurring. Without the
connection, a reset would occur because a watchdog signal on WDI would not occur in the required time frame. The Wake Up Pin provides the watchdog signal into the WDI Pin.
Battery VIN C1 CS8151 WDI VOUT C2 Microprocessor VCC
CDelay CDelay GND
RESET Wake Up
RESET
Output Stage Protection
Figure 7. Device Operation Without Watchdog Function Stability Considerations
The output stage is protected against overvoltage, short circuit and thermal runaway conditions (see Figure 8). If the input voltage rises above the overvoltage shutdown threshold (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180C (Typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.
> 50 V VIN VOUT
The output or compensation capacitor C2 (see Figure 9) helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability.
VIN C1* 0.1 mF VOUT CS8151 RESET RRST C2** 10 mF
*C1 required if regulator is located far from the power supply filter. **C2 required for stability.
IOUT
Figure 9. Test and Application Circuit Showing Output Compensation
Load Dump
Short Circuit
Thermal Shutdown
Figure 8. Typical Circuit Waveforms for Output Stage Protection
The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of
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CS8151
the capacitor will vary considerably. The capacitor manufacturers data sheet usually provide this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.
Calculating Power Dissipation In a Single Output Linear Regulator PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max)IQ
(1)
where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
RqJA + 150C * TA PD
(2)
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in equation 2 will keep the die temperature below 150C.
IIN VIN SMART REGULATOR(R) IOUT VOUT
} Control Features
IQ
Figure 10. Single Output Regulator with Key Performance Parameters Labeled
In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.
Heat Sinks
Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(3)
where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heatsink thermal resistance, and RqSA = the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers.
The maximum power dissipation for a single output regulator (Figure 10) is:
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CS8151
PACKAGE THERMAL DATA Parameter RqJC RqJA **Junction-Lead (#5) Typical Typical D2PAK-7 1.8 10-50* SOIC-14 23** 116 SOIC-16 18 75 Unit C/W C/W
*Depending on thermal properties of substrate. RqJA = RqJC + RqCA.
Battery VIN C1 CS8151 WDI VOUT C2 Microprocessor I/O VCC
CDelay CDelay GND
RESET Wake Up
RESET
I/O
Figure 11. Application Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
1000 100 10 CVOUT = 1 mF 1 0.1 0.01 CVOUT = 10 mF CVOUT = 47 mF Unstable Region 0 10 20 70 80 30 40 50 60 IOUT OUTPUT CURRENT (mA) 90 100 Unstable Region CVOUT = 47 mF CVOUT = 1 mF Stable Region
ESR (W)
Figure 12. CS8151 Output Stability with Output Capacitor Change
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CS8151
ORDERING INFORMATION
Device CS8151YDPS7G CS8151YDPSR7G CS8151YDWF16G CS8151YDWFR16G CS8151D2G CS8151D2R2G Package D2PAK-7 (Pb-Free) D2PAK-7 (Pb-Free) SO-16L (Pb-Free) SO-16L (Pb-Free) SO-14L (Pb-Free) SO-14L (Pb-Free) Shipping 50 Units / Rail 750 / Tape & Reel 47 Units / Rail 1000 / Tape & Reel 55 Units / Rail 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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CS8151
PACKAGE DIMENSIONS
D2PAK-7 (SHORT LEAD) DPS SUFFIX CASE 936AB-01 ISSUE A
K
A E S B H L P D G N M
TERMINAL 8
U
NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E G H K L M N P R S U V INCHES MIN MAX 0.396 0.406 0.326 0.336 0.170 0.180 0.026 0.036 0.045 0.055 0.050 REF 0.539 0.579 0.055 0.066 0.000 0.010 0.100 0.110 0.017 0.023 0.058 0.078 0 8 0.095 0.105 0.256 REF 0.305 REF MILLIMETERS MIN MAX 10.05 10.31 8.28 8.53 4.31 4.57 0.66 0.91 1.14 1.40 1.27 REF 13.69 14.71 1.40 1.68 0.00 0.25 2.54 2.79 0.43 0.58 1.47 1.98 0 8 2.41 2.67 6.50 REF 7.75 REF
V
R
C
SOLDERING FOOTPRINT*
9.5 0.374 3.25 0.128 C L 10.54 0.415 2.16 0.085 1.27 0.050
C L 3.8 0.150 1 0.96 0.038
SCALE 3:1 mm inches
8.26 0.325
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CS8151
PACKAGE DIMENSIONS
SO-16L DWF SUFFIX CASE 751G-03 ISSUE C
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1 16X
8
B TA
S
B B
S
h X 45_
M
8X
0.25
E
0.25
M
A1
14X
e
SEATING PLANE
T
C
DIM A A1 B C D E e H h L q
A
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L
CS8151
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE J
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
SOLDERING FOOTPRINT*
7X
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CS8151/D

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